Arrangement for converting decimal numbers into binary numbers or vice versa



Nov. 14, 1961 w HANDLER EFAL 3,008,633

ARRANGEMENT FOR CONVERTING DECIMAL NUMBERS INTO BINARY NUMBERS OR VICE VERSA Filed March 18, 1958 6 Sheets-Sheet 1 H Inventor: munmi lmmum .1 IM w-arra 46/4/20 y 4a A. W

Fur/v7 fits/r7 1961 w. HANDLER ErAL 3,008,638

ARRANGEMENT FOR CONVERTING DECIMAL NUMBERS INTO BINARY NUMBERS OR VICE VERSA Filed March 18, 1958 6 Sheets-Sheet 2 INVENTORS Wolfgang Hc'indler a I Hans-0H0 Leilich ATTORNEY Nov. 14, 1961 W. HANDLER El AL ARRANGEMENT FOR CONVERTING DECIMAL NUMBERS INTO BINARY NUMBERS OR VICE VERSA Filed March 18, 1958 I I I 6 Sheets-Sheet 3 FlG.lb.

INVENTORS Wolfgang Hfindlera Hons-Otto Leilich ATTORNEY Nov. 14, 1961 w. HANDLER EFAL 3,008,538

ARRANGEMENT FOR CONVERTING DECIMAL NUMBERS INTO BINARY NUMBERS OR VICE VERSA Filed March 18, 1958 6 Sheets-Sheet 4 INVENTORS Wolfgang Htindlera H Hons-Otto Lelllch o 2:11

ATTORNEY 3,008,638 ERS 6 Sheets-Sheet 5 Nov. 14, 1961 w HANDLER ETAL ARRANGEMENT FOR CONVERTING DECIMAL NUMB INTO BINARY NUMBERS OR VICE VERSA Filed March 18. 1958 J J m u f. H R n w Nk q n QQ Q k fi k k M w w w Nov. 14, 1961 Filed March 18. 1958 W. HANDLER Er AL ARRANGEMENT FOR CONVERTING DECIMAL NUMBERS INTO BINARY NUMBERS OR VICE VERSA 6 Sheets-Sheet 6 E INVENTORS Wolfgang Htindlera Hons-Otto Leilich ATTORNEY 3,lltl8,638 ARRANGEMENT FUR CONVERTENG DECIMAL NUMBERS INTU BINARY NUMBERS R VICE VERSA Wolfgang Handler and Hans-Otto Leilich, Eaclmang, Germany, assignors to Telefunken G.m.b.H., Berlin, Germany Filed Mar. 18, 1958, Ser. No. 722,209 Claims priority, application Germany Mar. 20, 1957 3 Claims. (Cl. 235-l55) This invention relates to an arrangement for converting decimal numbers into binary numbers or vice versa, more particularly for use in electronic computers and similar programme-controlled units. Computers and other apparatus operating in purely binary system require number conversion from and into the decimal system at the input and output, respectively, of the quantities involved in the calculating process. For this purpose various algorithms or calculating methods are known, according to which a computer is provided with a separate control unit which introduces the necessary calculating steps in the correct succession; alternately, there are provided in the computer iterative sub-programmes which contain, say, 60 orders or more, in order to call up in proper succession the elementaary operations corresponding to the calculating specification of the respective algorithm. Both methods have the disadvantage that the whole computer must be used for conversion purposes so that the apparatus cannot perform any other calculating operation during the conversion time. Furthermore it is necessary either to spend a considerable amount of money on control units, or to reserve a large portion of the store means for the sub-programme required, said portion being thus no longer available for the actual calculating work. Also, algorithms used for conversion in a purely binary apparatus are rather complicated and therefore require a large number of operations so that a considerable time has to be added to the actual calculating time.

It is an object of this invention to provide a new and improved apparatus for converting numerical information from one radix to another,

It is another object of this invention to provide a new and improved apparatus for the conversion of numerical information from decimal to binary notation.

It is a further object of this invention to provide a new and improved apparatus for converting numerical information from binary to decimal notation.

Other objects and advantages of this invention will become more apparent as the following description proceeds, which description should be considered together with the accompanying drawings, in which:

FIGURE 1 illustrates, in block form, a shift register used in the system of this invention;

FIGURE 1a shows the left end of a portion of the shift register of FIGURE 1, this portion being hereinafter identified as B;

FIGURE lb shows the middle portion of the shifting register, including the transition of the portion B to a portion'hereinafter identified as D;

FIGURE shows a tetrad of the register portion D, particularly the tetrad at the right end of the register;

FIGURE 2 illustrates, in block form, a correcting network according to the principles of this invention;

FIGURE 3 illustrates, in block form, a shift register and associated circuit elements for converting numbers with floating points from one radix to another; and

FIGURE 3a shows a binary counter, made up of conventional components, and having four binary positions.

atent O 3,008,638 Patented Nov. 14, 1961 The invention utilises a particularly simple algorithm which was already known but has never been used heretofore in a purely binary apparatus for conversion purpose, because it was not considered suitable (see Booth and Booth, Automatic Digital Calculators, London, 1956, page bottom). Application of this algorithm according to the invention requires only relatively simple connecting networks, very little expense on control means and no participation of the store capacity of the computer. Except for the aforementioned connecting networks the various calculating operations require a shift register only, so that it is possible to perform a conversion without utilising the whole apparatus; the invention is particularly advantageous when it is necessary to perform a conversion and a whole computer is not available.

The simple algorithm used will first be described briefly hereafter. A proper decimal fraction of the form N E k k r 3 Q I 1 is converted into a binary fraction of the form M B=Eb ,-2- (b =O,L) (L=binary one) by successively multiplying by 2. After the first multiplication, the first digit (carry over) before the decimal point indicates whether the factor /2=2 is present or not in the binary fraction. After the second multiplication, said first digit is shifted by one position toward left while a zero or a one appears now directly before the decimal point. This last-mentioned digit indicates in a similar way whether the factor A=2- is present or not in the newly-formed binary fraction. Step by step the whole binary number can thus appear on the left of the decimal point. In this process, the left-hand portion of the number (integer) must be repeatedly multiplied by 2 in the binary code (which means, shifted by one position to the left) while the right-hand portion (fraction) must be multiplied by 2 in the decimal code.

We have:

etc., and generally D.2"=(b .2 +b .2 b ,,.2-").2

The resulting binary number is shifted every time by n digits towards left before the virtual decimal point, while the digits d' d etc. are obtained by multiplying the number by 2 according to the arithmetic laws. The process is stopped when the binary number is equal to the decimal number with sufiicient accuracy. There is finally obtained:

M is to be determined in a suitable manner in accordance with N. Both representations of the number have about the same relative accuracy when 2 -10 For illustrative purpose it is shown therebelow how the proper decimal fraction 0.413 is converted step by step into a binary fraction:

a Q) TABLE 1 0. 0.415 0.0 0.826 0.0L 1.652 0.0LL 1.504 0.0LLO 0.608 0.0LLOL 1.216 OLLOLO 0 .452 0 OLLOLOO 0 864 0.0LLOLOOL 1.728 0.0LLOLO0LL 1.456 0 OLLOLOOLLO 0 912 Each arrow indicated occurrence of a decimal one which is transferred as a binary one (L) to the left-hand side. It will be appreciated that the process could be continued to infinity; for the afore-mentioned reasons it is however suitable to stop it at M (2 x10 In a similar manner, decimal integers are converted through gradual division by 2. For illustrative purpose there is shown hereafter conversion of the decimal inte- For application of the above-described algorithm there is provided an arrangement for converting decimal numbers into binary numbers or vice versa, which includes a two-section shift register, the first section thereof being used for reception of the decimal number in binary (e.g. tetrad) coded form for each decimal position, while the second section thereof is used for reception of the binary number. Moreover there is provided a device which shifts the number contained in one of said sections step by step into the other section, this being done by gradual multiplication by 2 (left shift) or division by 2 (right shift). Furthermore there is provided a decision network for checking the decimal section of the register, between any two one-digit shifts, on the occurrence of pseudotetrads or, possibly, carries over, and performing corresponding corrections on the respective tetrads. For converting a proper fraction, the right-hand section of the register may be used for reception of the decimal fraction coded in tetrads and the lefthand section for reception of the binary fraction, so that in converting a decimal fraction into a binary fraction, the latter is formed by the overflows of the tetrad representing the tenths of the decimal number, said overflows appearing on gradually multiplying by 2 (left shift). For converting an integer, the left-hand section of the register may be used for reception of the tetrad-coded decimal number and the right-hand section, for reception of the binary numher, so that during the conversion process of a decimal number into a binary number, the latter is formed by the remainders of the tetrad representing the unities, said remainders being transferred into the binary section on gradually dividing by 2 (right shift).

To make the description clearer, reference will be made hereafter to a left-hand and a right-hand register section, B and D respectively, this however implying no limitation. Each section of the register contains a series of digits, the left-hand section has a series of M binary positions and the right-hand section, a series of N decimal positions each consisting of four binary positions, according to the relationship Z zIO The sections may also be formed as two separate registers connected in any suitable manner, for example by means of a ring-shaped coupling.

In practice, the same register section will be used for decimal numbers and for binary numbers respectively, both when dealing with proper fractions and When dealing with integers. if, for example, the right-hand section of the register is always used for decimal numbers, care must be taken, when converting integers, that the right-hand end of the register should be connected to the left-hand end thereof so as to allow for the remainders of the division by 2 leaving the right-hand end to feed the binary section through the left-hand end thereof and for the overflows of the multiplication by 2 leaving the left-hand end to enter the decimal section again through the right-hand end thereof.

FIG. 1 illustrates diagrammatically such a register comprising a binary section B and a decimal section D. The latter consists of N=3 tetrads:l2 positions, the binary section of M=10 positions. Each position of the register may be represented in known manner by a flipflop circuit, such as those disclosed in A Transistor Reversible Binary Counter, by Robert E. Trent, in National Electronic Conference Proceedings, volume 8, 1952, on pp. 346357; and also in A Variable Binary Sealer, by D. B. Murray, in I.R.E. Transactions, EEO-4, of June 1955. These flip-flop circuits are interconnected to form a shift register so that a pulse coming from the pulse source R causes the register contents to be shifted by one position to the right, While a purse coming from the pulse source L causes said contents to be shifted by one binary position to the left. Moreover the fiip-fiop circuits in the decimal section are provided with input terminals (not shown in 1) which enable them to perform a change over in each individual flip-flop. The purpose of this arrangement is explained hereafter with reference to FIG. 2. The flip-flop circuits referred to in the specification are by no means intended to limit the invention. Any other static or dynamic bistable register element is suitable for the operations described herein. To simplify the description, the operation change over is also assumed in connection with the use of flipflop circuits with other elements. The operations set and clear may replace the change over.

Performance of the register will be illustrated by means of Table 3 which shows how the algorithm is used for converting a proper decimal fraction into a binary fraction as in Table 1, with application of the direct tctrad coding. Here again, there is denoted by B the left-hand section of the register where the binary fraction is built up gradually by left-shift, and by I, H and III the righthand section D of the register where the tenths, hundredths and thousandths of the decimal fraction 0.413 respectively are set in tetrad coding at the beginning of the operation.

TABLE 3 Step Part B I II III Dec.

01.00 0001. 001.1. .415 a Shifting .0 L000 OOLO OLLO l corr: none.

b .0 L000 0010 01.1.0 .826 a. Shifting cg: .OL 0000 OLOO LL00 2 I and III WW W WWW b .OL OLLO OLOL 00LO .652 a Shifting 00'. OLD LL00 LOLO OLOO 5.... I and II. W 'iWW W W b .OLL OOLL 0000 OLOO .504 a Shifting .OLLO OLLO 0000 L000 4 corr: none.

b .OLLO 0LLO 0000 L000 .608 a Shifting co: .OLLOO LL00 000L 0000 5 II and III. W WWW WW b .OLLOL 00L0 OOOL OLLO .216 a Shifting OLLOLO 0L00 OOLO LL00 6 corr: III. W WWW b I .OLLOLO 0L00 OOLL 00L0 .452 a Shifting .OLLOLOO L000 OLLO 0L00 7 oorr: none.

b .OLLOLOO L000 OLLO OLOO .864 a Shifting o0: .0LLOLO0L 0000 LL00 L000 8 I an I. WW WWW b .OLLOLOOL OLLL 00L0 L000 .728 a. Shifting co: .OLLOLOOLO LLLO OLOL 0000 9 I and III. W W W WW b 4 .OLLOLOOLL 0L00 OLOL 0LLO .456 10. a Shifting .OLLOLOOLLO L000 LOLO LL00 Each step 1, 2, 3 consists of two parts a and b; a shift of one position toward left occurs during the first part, a, and a check on the occurrence of pseudo-tetrads or carries over from one tetrad to the next one, as well the impulse source L or R, as the case may be. This also ensures the correct positioning of the decimal point after conversion.

Reverse conversion of a binary fraction into a decimal as a corresponding correction, are performed during the 5 fraction may also be performed in a corresponding mansecond part, b. Pseudo-tetrads and carries over occur ner, succession of both step parts a and b being interwhen, before the shift, a tetrad contained a decimal changed and shifts toward right replacing shifts toward digit ;5. Therefore, no correction is required after the left (division by 2). The binary number is thus confirst shift toward left (step 1a) and the right-hand section tained in section B and a determination is first made of the register contains 0.826. After the second shift Whether in one of the positions in which the shifting had toward left (step 201), a L is transferred into the section occurred (this can, at first, be only the least significant B and the pseudo-decimal LL00 appears in the tetrad III. binary position) there is a L, and the number 0LLO=6 Tetrads I and III must be corrected by adding the amount is subtracted in the corresponding adjacent right-hand 6=0LLO (step 2b) to each of them producing changes in tetrads. The number is then shifted to the left by one those binary digits below which W appears in Table 3, binary digit, is again tested, and, if necessary, corrected so that the number 0.652 appears now in tetrad-coding in as explained above. the right-hand section of the register. The carry from Table 3a illustrates a numerical example (0.LLOL= tetrad III produces a change in one binary digit of tetrad 0.8125) of the above:

TABLE 3a t i D E R B P T I II III L L 0 L O O 0 0 0 0 l 3. COIIZ none b Shifting LLOLOOOOO 0 2 a GOIIZ none b Shifting LLOLOOOO 00 3 a COIII none b Shifting LLOLOOO 000 4 9. Cor]?! none b Shifting LLOLOO 0000 5 a GQIIZ none b Shifting LLOLO 0000 0 6 a COIIZ none b Shifting LLoL 0000 00 a. corr: I O L L 0 7 L L 0 0 L 0 L 0 0 0 b Shifting LLo OLOL 000 a corrzII 0LLO 8 L L 0 0 L 0 0 L 0 L 0 b Shifting LL OOLO oLoL 0000 a corr:IandIII -OLLO -OLLO 9 L 0 L L 0 0 0 L 0 0 L 0 L 0 b Shifting L OLLO 00L0 0LOL a. corr: I O L L O 10 L 0 0 0 0 0 0 L 0 0 L 0 L b Shifting L000 000L OOLO (L II, as shown in the table. After the third shift (step 3a), The aforementioned corrections which comprise the 0L0 appears in the binary section B. Because of the addition of OLLO are effected according to the invention pseudo-decimals, a correction is necessary in the tetrads by means of a decision network. The correction depends I and II (step 3b), and so on. At the end of the process, upon the shift direction of the algorithm considered- In the M-position binary number appears in the left-hand the case of a shift toward left, which occurs when a proper section of .the register, while the decimal remainder redecimal fraction'is converted into a binary fraction, or a mains in the right-hand section. This process will be carbinary integer into a decimal number, a correction in mulried on until said remainder can no longer yield any eifectiplication by 2 is only required when one of the numtive digit for the binary number, though it still includes bers 5, 6, 7, 8 or 9 appears previously in the tetrad. If three decimal numbers according to the relationship the tetrad contains the numbers 0, 1, 2, 3 or 4 before the 2 -l0 To be sure to stop the process at the right shift, no correction is required. In the direct tetrad codmoment, there is provided a counter unit (not shown in ing, which is given herein by way of example, the new the drawing) having a capacity equal in number to the tetrad contains after the shift either the double value 2, 4, M number of positions of the binary section B. This 6 or 8, or the value 3, 5, 7 or 9 in the case where a carry counter, after M shifting steps, produces a signal which over from the next-lower tetrad (right adjacent tetrad) is suppresses the further generation of shifting impulses from to be added. It is different in the case where the tetrad contained one of the numbers 5, 6, 7, 8 or 9. A carry over must be effected on to the next tetrad (left adjacent tetrad) after each shift in the final result. A general survey appears in the following table:

The corresponding decimal numbers are in the first line. The corresponding tetrad in direct coding (with the values 8, 4, 2, l) is in the second line. The third line shows the tetrad after a shift by one position toward left (multiplication by 2). This causes the first digit of each tetrad to be carried over as a unity into the next higher tetrad. In the fourth line there are shown the corrected digit values. In the fifth line the letter W indicates in which binary position a change over has taken place. This letter W appears also in Table 3 at every step between parts a and parts b and indicates a change over.

If the various flip-flops of a tetrad are denoted by x .14, x x according to their binary position values, and the flip-flop corresponding to the unity of the next (left) tetrad into which a carry over may be transferred is denoted by x it will be seen that the position x of said tetrad is unimportant for the correction to be performed. But, on correcting, the position x (x of the next tetrad, Heft) must be considered together with the positions x x and x A decision circuit performing the corrections indicated in the previous tables must therefore effect a change over in some positions x (k=2, 4, 8, u) in other words, convert a one into a zero or a zero into a one, depending on whether a zero or a one is set in some other positions x, (i=2, 4, 8, it). For the numbers 5, 6, 7, 8 and 9 (before the shift) there can be found particular rules which are given in Table 5, lines A to D. X denotes the condition of the register when the respective digit x, is one (L) and E, the condition of the register when said digit is a zero Corresponding relationships are obtained when converting a binary fraction into a decimal fraction, the correction being performed in the first part of each step and the shift toward right in the second part of each step. The relationships prevailing herein are given in Table 5, lines E to H. The decimal numbers appearing in the respective tetrad be fore (A to D) and after (B to H) the shift are given in the last column:

TABLE 5 A, if X & X then change over x x x (5 and 7) B, if X & X & Y then change over x,,, x x x (6) C, if X & 55 then change over x x (8) D, if X & X then change over x x (9) E, if X & X & Y then change over x,,, x x (5 and 7) P, if X & 5Z & X then change over 1 8, 4 2 G, if X & X & X then change over x x (8) H, if X & X then change over x x (9) It can be seen that in the case where a 5 or a 7 appears in the tetrad before the shift, the same relationship is valid.

A correcting network performing the corrections indicated above is represented diagrammatically for one tetrad in FIG. 2. The various positions of the tetrad which may be represented by flip-flop circuits are denoted by x x x x and x,,, x belonging to the next higher tetrad of the register where it forms the digit x Each flip-flop has two output conductors, one of them, X carrying voltage when the condition L(X prevails, the other carrying voltage when the condition ()(K) prevails except for x which has output conductor L(X only. In accordance with the operations derived from the above table, these output conductors lead to andgate circuits A D and E H, which can be designed in known manner as relay, tube, transistor, ring core or diode circuits. Some typical gate circuits are shown in High-Speed Computing Devices, by the Staff of Engineering Research Associates, Inc., published by McGraw- Hill Book Co., in 1950, pp. 37-45. Every such gate has an input for correction pulses supplied by the source 1 for the gates A D and by the source 2 for the gates E H. When a shift toward left (multiplication by 2) is preformed in the first time of a step, a pulse from the correction pulse control source 1 is fed to the gates A D in the second time of said step. When a shift toward right (division by 2) is performed, a pulse from the source 2 is fed to the gates E H. The outputs of gates A H are connected to the corresponding control inputs J, K, L, M of the flip-flops x according to the aforementioned relationships A H, in such a manner that a change over occurs in the right flip-flops. It will be appreciated that such a circuit embodies the aforementioned connections A H.

Referring now to FIGURES 1a, 1b, and 10, FF show the flip-flops of the individual register elements. Each flip-flop has two inputs c and c and two outputs a and 0 for the Zero (0) and one (L) bits of information. The elements are, in a known manner, so interconnected by a network made up of AND-circuits A and OR-circuits 0, that when an impulse arrives at the line L, the information is shifted leftwardly by one element, and when an impulse arrives at the line R, the information is shifted rightwardly by one element. As shown in FIGURE 1a, the lines L' and R are connected with the impulse source L and R, respectively (FIGURE 1). Furthermore, the lines L' and R are each connected to an impulse counter C which, by transmitting a stop command, turns off the respective impulse source after N steps.

FIGURE 1b additionally shows the connections I, K, L, M, of the output lines of a correcting network according to FIGURE 1 to the inputs of the flip-flops of the first tetrad I via additional AND-circuits A, as well as the above-mentioned OR-circuits 0. When an impulse is applied to one of these lines, the corresponding flipflop will change its position, i.e., zero becomes one and one becomes zero. Also shown are the outputs X,,, X X X X X X which act as inputs for the correcting network illustrated in FIGURE 2.

Other embodiments of registers according to the invention can also be carried out, wherein the process which requires two parts to each step in the aforementioned example can be effected in one part only. In such a case, however, it is generally necessary to se and clear the flip-flops representing various digits of the register, instead of using a change over" as in the above described example. Other methods of coding the decimal numbers require obviously other correcting networks, the function of which is determined by the special method involved.

It will be appreciated that a shift register of the aforedescribed type can be used to perform the following conversions (a) Conversion of proper decimal fractions into binary fractions and vice versa First, the decimal number in direct tetrad coding is located in the right-hand section of the register. The

decimal point lies virtually between the two halves of the register. The number is gradually transferred to the left-hand section in the above-mentioned manner and thereby converted into a binary number. The number of steps is preferably equal to the binary capacity of the left-hand section. To convert proper binary fractions into decimal fractions the process is carried out in the reverse direction.

(b) Conversion of decimal integers into binary numbers and vice versa First, the number in direct tetrad coding is located in the right-hand section of the register. The decimal point lies virtually on the right, at the endof the right-hand section. Said end is coupled to the left-hand end of the left-hand section. During the conversion process the number is derived gradually from the register on the right thereof and fed again to the left-hand section from the left. The number of steps should here also be equal to the binary capacity of the left-hand section of the register, so that at the end of the conversion process the number is located at the proper place in the left-hand section. To convert binary integers into decimal numbers the process is carried out in the reverse direction.

For every shift toward left (multiplication by 2) the corresponding correction pulse source 1 must be actuated, and reversely, for every shift toward right (division by 2) the corresponding correction pulse source 2 must be actuated. In the first case, shift is performed first, then correction; in the second case, operations are reversed.

According to a further embodiment of the invention the register shown diagrammatically in FIG. 1 can be so completed as to convert numbers in half-logarithmic representation (floating point representation) too, this enabling mixed numbers with an integer and a fractional part to be converted. For this purpose, additional counters for the exponents must be provided. In floating point representation, a decimal number appears as D=d.10 where d is the decimal mantissa and p the integer exponent of base 10. By selecting p correspondingly, ld| 1 is ensured. A binary number B is represented in floating point representation as follows: B=b.2 where b is the binary mantissa and q the integer exponent of base 2.

FIG. 3 shows a register suitable for converting numbers in floating point representation. Counters P (for the decimal exponent p) and Q (for the binary exponent q) are added to the units B, D, R and L already described wi-th reference to FIG. 1. Counters are discussed in substantial detail in High-Speed Computing Devices, pp. 12-31. There are also added two further pulse sources 4R and 4L, through which the whole register contents can be shifted by four positions toward right or toward left. Such a shift results in a division or a multiplication by respectively in the decimal section D of the register. The various pulse control sources R, L, 4R and 4L are controlled by a control unit St, in accordance with the algorithm to be disclosed hereafter with reference to a few examples. From the control unit St, control conductors 1, 2, 3, 4 lead to the various pulse sources L, R, 4L, 4R and read out conductor 6 leads to the first binary position of the register section B while read out conductor 6 is connected to the first tetrad of register D. A further read out conductor 7 leads to the counter P.

Operation of this arrangement will be explained sepanately for the case p 0 and for the case p 0.

In both cases, when the conversion process of a decimal numberinto a binary number starts, the decimal mantissa d is located in the right-hand section D of the shift register, for example in direct tetrad coding, as already explained above. The exponent p is in the decimal exponent counter P. The left-hand section B of the register is used once more to receive the binary mantissa b which is built up step by step, while at the end of the 10 conversion process, the counter Q will contain the binary exponent q.

Conversion is performed in two operative stages; in the first one, there is effected a normalisation which comprises breaking up the decimal exponent located in the counter P through simultaneous transformation of d and transferring it as a binary exponent into the counter Q Which is positioned at Zero at the beginning of the normalisation process. This is done in a different manner, depending on whether p 0 or p 0, i.e., whether the number in the counter is positive or negative. In order to determine this, the most significant position can be used to represent the algebraic sign. Accordingly, such position can then not be used for positive numbers, i.e., the counter must have a number of positions which are greater by one than the number of digits of the largest number which is to be handled. If with such a counter one starts with the position Zero and counts backwards one step, then in the case of a decimal counter, a series of nines will appear, whereas with a binary counter a series of ones will appear. The number 9, or 1, in the most significant position is thus indicative of the fact that a negative number is stored in the counter, this information being given in the so-called complementary form. Thus, the question of whether p 0 or p 0, can readily be determined at the counter P or Q by reading out the most significant position.

In order to illustrate the above, reference is made to FIGURE 3a which is a binary counter having four binary positions I, II, III, IV, and which is made up of conventional AND-circuits A, OR-circuits 0, and flip-flops FF. This counter will count backward one step whenever an impulse is applied to the terminal (l), and forward one step whenever an impulse is applied to the terminal (+1). If care is taken that the absolute value stored in the counter is never larger than 2 1=7, the position 1V will always be zero when a positive value is stored in the counter, and always be one when a negative value is stored, the positions I, II, and III then representing the stored number in its complementary form.

If p 0, the process starts with continuous multiplica tions by 2, in other words, with shifts by one position to ward left followed by corrections of the pseudo-tetrads and carries over, the pulse source L being actuated via the control conductor 1. The number of these multiplications is fed to the counter Q via the conductor 8 and subtracted from Zero in said unit. Whenever a pulse is applied to L to cause a left shift of the register, a pulse is also applied through line 8 to the counter Q to step the counter backward one count. As soon as on overflow occurs from the register section D into the register section B- this being reported to the control unit St by the read out conductor 6- the succession of multiplications by 2 is stopped and the pulse source 4R is actuated Via the control conductor 4 and causes a shift by four positions toward right, namely a division by 10, to occur in the register. At the same time the negative exponent located in the counter P is increased by 1 via the conductor 9. Then, multiplications by 2 are resumed and the number in the counter Q is simultaneously decreased by 1 every time, till the next overflow occurs. This change over will go on until the exponent zero appears in the counter P. This condition is reported to the control unit St via the read out conductor 7 and said unit then initiates the second operative stage which is carried out exactly as already explained in details for conversion of ordinary decimal fractions with reference to Table 3. The final binary exponent q is now to be found in the counter Q After the M further multiplications by 2, the binary mantissa appears in the register section B and the binary exponent in the counter Q, and it will be noted in this respect that counters P and Q are no longer connected during the second operative stage. Table 6 shows an example of calculation for converting Result! O.OOLOOOOOLL.2-

The number M of positions in the register section B is assumed to be 10 (10 -2 For better understanding, the decimal numbers are listed in column D not in tetradcoded form but in decimal writing. The succession of operations to be effected, multiplications by 2 (.2), divisions by 10 (:10) are listed in column Op. The columns P and Q indicate the condition of the respective counters at the instant considered. At the beginning of the calculation the contents of the binary section B of the register are zero, and the number 0.1 in tetrad-coded form is located in the decimal section D. The contents of the decimal exponent counter P are -2 and those of the binary exponent counter Q are zero. The number of multiplications by 2 is interrupted for the first time when the number 1.6 appears in the decimal register, transferring a L into the binary section B. However, the following division by 10 (shift of four positions toward right) causes this L to go back into the decimal section D. At the end of the first operative stage, when the contents of the counter P are brought to zero, the number 0.128 is found in the decimal section D (of course, in tetradcoded form) and the number 7 in the binary exponent counter Q. There follows the second operative stage, wherein continuous multiplications by 2 are performed and the overflows which occur are shifted into the binary section B of the register. After M: 10 steps, the calculasion is over; the result is 0.l.1O' =0.OL00000LL.2

Conversion of integers or mixed decimal numbers in floating point representation, wherein |di 1 and p l, is performed in a corresponding manner, the decimal mantissa introduced in the decimal section being during the first operative stage continuously divided by 2 (control of R via conductor 2.), and multiplied by 10 (control of 4L vi a conductor 3) each time the first decimal digit disappears, i.e. when a zero appears in the first left-hand tetrad of section D (report to St via conductor 5).

At the beginning of the conversion process, the decimal exponent p is brought again into the decimal exponent counter P. At each division by 2 the number in the binary exponent counter Q is increased by 1 via the conductor and at each multiplication by 10 the number in the counter P is decreased by 1 via the conductor 11. This type of operation will continue until the number 0 appears in the counter P-this being again reported to St via the conductor 7. In the second stage, operations run as in Table 3, the binary mantissa being formed in the left-hand section B of the register from the right-hand end thereof. Counters P and Q are not operating during this second stage. A calculation example in the form of a table needs not be given since this last-mentioned process can easily be understood from the preceding description.

The reverse case, i.e. conversion of a binary number into a decimal number, is performed in two steps in a corresponding manner, the binary exponent counter Q being first brought to Zero by continuous multiplication, or division, by 2 and division, or multiplication, by 10 (according to the value of q: 1 or 1) at the same time the decimal exponent being formed in the counter P. There is also provided a further read out conductor 12, which reports the zero in Q to control unit St and thereby changes over to the second operative stage that is performed in reverse succession, as aforementioned, with respect to the conversion of decimal numbers into binary numbers.

In order to achieve an accurate conversion, it can be necessary to have a few more decimal positions (about four) at the right-hand side of the register section D. The number of additional decimal positions required depends on the admissible exponent range. Especially, the left-hand side of the left-hand register section B may be used for this purpose, since during the first part (normalisation) of the conversion process, no digits are located in said section.

According to the specification so far described, the binary mantissa lies in the range 0.l b 1 after the conversion process. However, the normalisation 0.5 b 1 is usual. If it is desired to achieve this usual normalisation small shifts must be performed by means of the counter Q and this, at the end of the conversion process. Such a normalisation with conventional means gives rise to no additional difficulties; if the binary number b is smaller than 0.5, a zero will appear at the most significant position of the register B because the value of this position is equal to /2. This can readily be interrogated via the line 6, shown in FIGURE 3, and the read-out result, i.e., zero, is used to continue to shift the information rightwardly in a stepwise manner until a one appears in the most significant position of the register B. The number of these rightward shifts, each of which, of course, represents a multiplication by 2, must be subtracted in the counter Q. For example: the number 1 can be represented in a binary form as (LL-2 A Zero will then appear at the most significant position of the register B and a 3 will appear in the counter Q. But the normalized representation should read 0.L'2 and then a one Will appear in the most significant position of the register B as Well as in the counter Q. The one in register B is thus rightly displaced by two positions, and at the same time the contents of the counter Q has been reduced by 2.

Beside the aforementioned advantages of relieving the computer and thereby saving time, the arrangements according to the invention have a furhter advantage in that they can be used as decimal indicator devices in a binary computer. For the purpose of testing new programs or the computer itself, the output unit can be coupled to the indicator device without having to interrupt the calculating process itself.

We claim:

1. An arrangement for converting decimal numbers into binary numbers and binary numbers into decimal numbers, comprising, in combination: a two-section shift register made up of binary register elements and having a first section for storing signals representative of a decimal number in a binary-coded form and a second section for storing signals representative of a binary number, at least the most significant register element of said first section being connected to the least significant register element of said second section, means for shifting the signals representative of the number from the first register section into the other through gradual multiplication (shift toward left) and from the second register section into the first by division (shift toward right) by 2; and means connected to the register elements of said first section, including the least significant one of said second sec. tion, for testing signals representative of pseudo-decimals and overflows occurring between two shifts by one position and for feeding correction signals to those of said 1 3 register elements which according to the test result must be changed into their other state.

2. An arrangement according to claim 1 wherein the right-hand section of said shift register receives the coded decimal number and the left-hand section receives the binary number, wherein the right-hand end of the register is coupled to the left-hand end thereof in such a manner that when converting a decimal integer into a binary integer, the latter is formed in the left-hand section by the remainders resulting from gradual division by 2, said remainders leaving the right-hand end of the decimal section and entering the left-hand end of the binary section, and when converting a decimal fraction into a binary fraction the latter is formed in the left-hand section by the overflows resulting from gradual multiplication by 2, said overflows leaving the left-hand end of the decimal section and entering the right-hand end of the binary section.

3. An arrangement according to claim 2 for converting numbers in floating point representation having a mantissa smaller than one, further comprising a counter for the decimal exponent, a counter for the binary exponent, and a control unit which, when converting a decimal number having a decimal exponent p l or p l respectively into a binary number, performs gradually divisions or multiplications by 2 respectively, and a multiplication or a division by 10 respectively on the occurrence of a zero within or a carry over from the most significant decimal position respectively, this being done under simultaneous increase or decrease respectively of the contents of the counter for the binary exponent by one unity at every operation by 2 and simultaneous decrease or increase respectively of the contents of the counter for the decimal exponent by one unity at every operation by 10 until a zero appears in said last-mentioned counter thereby initiating an operation according to claim 2.

References Cited in the file of this patent UNITED STATES PATENTS 2,444,042 Hartley et a1. June 29, 1948 2,647,689 Bowyer et a1 Aug. 4, 1953 2,860,831 Hobbs NOV. 18, 1958 OTHER REFERENCES Mauchly-Conversion Between Binary and Decimal Number Systems, Theory and Techniques for Design of Electronic Digital Computers, University of Pennsylvania (June 1948). Lecture 25 (pages 251 to 258, pages 252 and 25-3 relied upon). 

